1. Technical Field
The present invention relates to microprocessors and, in particular, to mechanisms for managing data in a register file.
2. Background Art
Modern processors include extensive execution resources to support concurrent processing of multiple instructions. A processor typically includes one or more integer, floating point, branch, and memory execution units to implement integer, floating point, branch, and load/store instructions, respectively. In addition, integer and floating point units typically include register files to maintain data relatively close to the processor core.
A register file is a high speed storage structure that is used to temporarily store information close to the execution resources of the processor. The operands on which instructions operate are preferentially stored in the entries (xe2x80x9cregistersxe2x80x9d) of the register file, since they can be accessed more quickly from these locations. Data stored in larger, more remote storage structures such as caches or main memory, may take longer to access. The longer access times can reduce the processor""s performance. Register files thus serve as a primary source of data for the processor""s execution resources, and high performance processors provide large register files to take advantage of their low access latency.
Register files take up relatively large areas on the processor""s die. While improvements in semiconductor processing have reduced the size of the individual storage elements in a register, the wires that move data in and out of these storage elements have not benefited to the same degree. These wires are responsible for a significant portion of the register file""s die area, particularly in the case of multi-ported register files. The die area impact of register files limits the size of the register files (and the number of registers) that can be used effectively on a given processor. Although the number of registers employed on succeeding processor generations has increased, so has the amount of data processors handle. For example, superscalar processors include multiple instruction execution pipelines, each of which must be provided with data. In addition, these instruction execution pipelines operate at ever greater speeds. The net result is that the register files remain a relatively scare resource, and processors must manage the movement of data in and out of these register files carefully to operate at their peak efficiencies.
Typical register management techniques empty registers to and load registers from higher latency storage devices, respectively, to optimize register usage. The data transfers are often triggered when control of the processor passes from one software procedure to another. For example, data from the registers used by a first procedure that is currently inactive may be emptied or xe2x80x9cspilledxe2x80x9d to a backing store if an active procedure requires more registers than are currently available in the register file. When control is returned to the first procedure, registers are reallocated to the procedure and loaded or xe2x80x9cfilledxe2x80x9d with the associated data from the backing store.
The store and load operations that transfer data between the register file and backing store may have relatively long latencies. This is particularly true if the data sought is only available in one of the large caches or main memory or if significant amounts of data must be transferred from anywhere in the memory hierarchy. In these cases, execution of the newly activated procedure is stalled while the data transfers are implemented. Execution stalls halt the progress of instructions through the processor""s execution pipeline, degrading the processor""s performance.
The present invention addresses these and other problems related to register file management.